Image sensor chip

ABSTRACT

An image sensor chip includes a semiconductor layer intended to receive illumination on a back face and comprising a matrix of pixels on a front face. An interconnection structure is arranged on the front face and a carrier is attached to the interconnection structure with a first face of the carrier facing the front face. An annular trench, arranged on a perimeter of the image sensor chip, extends from a second face of the carrier through an entire thickness of the carrier and into the interconnection structure. A via opening, arranged within the annual trench, extends from the second face of the carrier through the entire thickness of the carrier to reach a metal portion of the interconnection structure. The via opening an annual trench are lined with an insulating layer. The via opening include a metal conductor making an electrical connection to the metal portion.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional application from U.S. patentapplication Ser. No. 15/600,962 filed May 22, 2017, which claims thepriority benefit of French Application for Patent No. 1661440, filed onNov. 24, 2016, the disclosures of which are hereby incorporated byreference in their entireties.

TECHNICAL FIELD

Embodiments relate to an image sensor chip and a method for themanufacture thereof.

BACKGROUND

A back-illuminated image sensor chip comprises a semiconductor layer,one face of which, referred to as the front face, is covered with aninterconnection structure, and the face of which that is opposite thefront face, referred to as the back face, is intended to receiveillumination. The chip comprises a matrix of pixels, formed in and onthe semiconductor layer, elements of which, such as transistors, areformed on the side of the front face and are connected to each other viathe interconnection structure.

A chip of this kind is manufactured from a semiconductor die or layer.In practice, a plurality of identical chips are formed simultaneously inthis die, which is then sliced in order to obtain individual chips.Before slicing, a handle or carrier is bonded to the side of theinterconnection structures formed on the front face of the semiconductordie, and then the die is thinned from its back face. After thinning ofthe semiconductor die, for each chip, conductive connecting vias areformed through the handle, as far as portions of the upper level ofmetallizations of the interconnection structure of this chip. Thesemiconductor die provided with the handle is then sliced in order toobtain individualized chips.

In a chip manufactured in the manner described above, after the step ofslicing or sawing, delaminations may be observed at the bondinginterface of the handle on the interconnection structure. Thesedelaminations extend from the edges of the chip and may propagate over alarge part of the bonding interface. This may result in malfunctioningof the chip, in particular on account of rupturing of one or moreconductive connecting vias.

There is a need in the art for a back-illuminated image sensor chipcomprising means for preventing the propagation of delaminations at thebonding interface of the handle on the interconnection structure. Itwould also be desirable to have a method for manufacturing a chip ofthis kind that comprises few or no additional steps with respect to aconventional manufacturing method.

SUMMARY

An embodiment provides an image sensor chip comprising a semiconductorlayer intended to receive illumination on the side of its back face andcomprising a matrix of pixels, an interconnection structure arranged onthe front face of the semiconductor layer and electrically connectingthe elements of the matrix of pixels to each other, a carrier arrangedon the interconnection structure, a first face of said carrier being onthe side of the front face, and an annular trench arranged on theperimeter of the chip, said trench extending from the second face of thecarrier through the entire thickness of the carrier.

According to one embodiment, the carrier comprises a first layer ofsilicon oxide at its first face, the trench passing through the firstlayer.

According to one embodiment, a second layer of silicon oxide is arrangedon the interconnection structure, the first face of the carrier isarranged on and in contact with the second layer, and the trench extendsthrough all or part of the thickness of the second layer.

According to one embodiment, the chip comprises conductive viasextending from the second face of the carrier and passing through thecarrier as far as portions of a level of metallizations of theinterconnection structure.

According to one embodiment, the trench is not as deep as the vias.

According to one embodiment, the trench surrounds all of said vias.

According to one embodiment, the trench does not penetrate into theinterconnection structure.

Another embodiment provides a method for manufacturing image sensorchips, comprising the following successive steps: a) providing a wafercomprising a semiconductor die, interconnection structures arranged on afront face of the semiconductor die, matrices of pixels formed in thesemiconductor die, each chip comprising a matrix, elements of which thatare formed on the side of the front face being connected to each othervia a corresponding interconnection structure, b) bonding, on the sideof the interconnection structures, a first face of a handle to thewafer, c) for each chip, engraving, from the second face of the handle,an annular trench on the perimeter of the chip, the trench passingthrough the entire thickness of the handle, and d) slicing the waferinto chips, the edge of each chip being arranged beyond the annulartrench of said chip.

According to one embodiment, in step b), a first layer of silicon oxideis formed at the first face of the handle, and, in step c), for eachchip, the annular trench is engraved through the first layer.

According to one embodiment, in step a), a second layer of silicon oxideis formed on the interconnection structures, and, in step b), the firstface of the handle is bonded on the second layer, the trench of eachchip being engraved through all or part of the thickness of the secondlayer.

According to one embodiment, the method furthermore comprises, in stepc), the formation of conductive vias comprising the following successivesteps: for each chip, engraving holes from the second face of the handlemade of silicon as far as portions of a level of metallizations of theinterconnection structure of this chip, forming an insulating layer onthe side of the second face of the handle, said insulating layercovering the walls and the base of the holes and of the trench of eachchip, removing the portions of the insulating layer at the base of theholes, and forming a conductive layer on the walls and the base of eachhole. According to one embodiment, the trenches and the holes areengraved simultaneously.

According to one embodiment, in step c), the engraving of the trenchesis interrupted before the interconnection structures.

According to one embodiment, in step b), after bonding of the handle,the semiconductor die is thinned from its back face.

According to one embodiment, between steps c) and d), a transparentcarrier is bonded to the wafer, on the side of the back face of thesemiconductor die, the handle then being thinned from its second face.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features and advantages will be disclosed in detail inthe following description of particular embodiments, which is given in anon-limiting manner, in relation to the appended figures, in which:

FIGS. 1A to 1D schematically illustrate successive steps of an exampleof a method for manufacturing a back-illuminated image sensor chip;

FIG. 2 illustrates an embodiment of a method for manufacturing aback-illuminated chip; and

FIG. 3 is a plan view of a chip obtained using the method of FIG. 2.

DETAILED DESCRIPTION

Like elements have been denoted using the same references in thedifferent figures and, moreover, the various figures are not drawn toscale. For the sake of clarity, only those elements that are useful forunderstanding the embodiments described have been shown and aredetailed.

In the following description, the terms “below”, “upper”, “lower” etc.refer to the orientation of the elements in question in thecorresponding figures. Unless indicated otherwise, the terms“substantially” and “approximately” signify to within 10%, preferably towithin 5%.

FIGS. 1A to 1D illustrate successive steps of an example of a method formanufacturing back-illuminated image sensor chips. More particularly,these figures are schematic cross-sectional views of a portion of one ofthe chips manufactured using this method, it being understood that, inpractice, a plurality of identical chips are manufactured simultaneouslyfrom one and the same semiconductor die or layer.

In the step in FIG. 1A, at the bottom in this figure, matrices of pixels1 have been formed on the side of the front face F1 of a semiconductordie 3, for example made of silicon, each chip 5 comprising a matrix ofpixels 1. An interconnection structure 7 has been formed on the frontface F1 of the semiconductor die 3. The interconnection structure 7comprises levels of metallizations, for example four levels M1, M2, M3and M4 of metallizations, embedded in insulating layers and connected toeach other by conductive vias. Each chip 5 comprises an interconnectionstructure 7 for connecting the elements of its matrix of pixels 1 toeach other, for example transistors 9, formed on the side of the frontface F1 of the semiconductor die 3. In practice, the interconnectionstructures of all of the chips of the semiconductor die 3 are formedsimultaneously. Optional insulating layers 11, 13, 15 and 17 have beenformed successively on the upper face of the interconnection structures7.

The assembly consisting of the semiconductor die 3, the interconnectionstructures 7 arranged on its front face F1, and the optional layers 11,13, 15 and 17 formed on the interconnection structures forms a wafer 19.

By way of example, the thickness of the die 3 may be between 600 μm and1 mm. The thickness of the interconnection structures 7 may be between 1μm and 5 μm, for example 2 μm. The layer 11 is, for example, a layer ofsilicon nitride, the thickness of which may be between 20 and 100 nm,for example 40 nm. The insulating layer 13 is, for example, a layer ofphosphorus-doped silica, or PSG (phosphosilicate glass), the thicknessof which may be between 100 and 500 nm, for example 250 nm. The layer 15is, for example, a layer of silicon nitride, the thickness of which maybe between 250 nm and 750 nm, for example 500 nm. The layer 17 is, forexample, a layer of silicon oxide, the thickness of which may be greaterthan 0.5 μm, or even greater than 1 μm, for example 2 μm. The layer 17is formed, for example, by deposition, for example by chemical vapordeposition or CVD, for example from tetraethoxysilane (TEOS).

With continuing reference to the step in FIG. 1A, at the top in thisfigure, a handle or carrier 21 made of silicon is provided. The handle21 comprises an optional layer of silicon oxide 23 arranged at its lowerface F3. The thickness of the layer of silicon oxide 23, for exampleformed by thermal oxidation, may be between 20 and 50 nm, for example 30nm.

In the step in FIG. 1B, the handle made of silicon 21 has been bonded tothe wafer 19 by molecular bonding, on the side of the interconnectionstructures 7. More particularly, in this embodiment, the layer ofsilicon oxide 23 of the handle 21 has been bonded to the layer ofsilicon oxide 17 of the wafer 19, the two layers 23 and 17 thus being incontact with each other. The wafer 19 provided with the handle 21 hasbeen flipped, and then the semiconductor die 3 has been thinned from itsback face F2, for example to a thickness of between 2 and 10 μm, forexample 5 μm.

Optional color filters 25 have been formed on the back face F2 of thethinned die 3, facing the matrix of pixels 1 of each of the chips 5.Each filter 25 has been covered with an optional microlens 27, eachmicrolens 27 being associated with a pixel of a matrix 1.

In the step in FIG. 1C, a carrier 29 that is transparent to the raysintended to be received by the pixels of the chips 5 has been bonded tothe wafer 19, on the side of the back face F2 of the thinnedsemiconductor die 3. The carrier 29, for example made of glass, may havea thickness of between 200 and 700 μm, for example 500 μm. The wafer 19provided with the carrier 29 and with the handle 21 has been flipped.The handle 21 has then been thinned from its upper face F4 to athickness that makes it possible to produce conductive connecting viasthat pass through the entire thickness of the handle 21. By way ofexample, the handle 21 is thinned to a thickness of less than or equalto 150 μm, for example less than or equal to 70 μm.

In this embodiment, the transparent carrier 29 is bonded to the wafer 19by means of a layer of adhesive 31, for example a polymer adhesive. Theadhesive 31 is arranged on the side of the back face F2 of thesemiconductor die 3, at the periphery of each chip 5, so as not to coverthe microlenses 27 and affect the operation thereof. In one variantembodiment, the microlenses 27 are omitted and the adhesive 31 may thenbe provided over the entirety of the back face F2 of the semiconductordie 3.

In the step in FIG. 1D, for each chip 5, conductive connecting vias 33have been formed through the handle 21, as far as portions of the upperlevel M4 of metallizations of the interconnection structure 7 of thischip 5. A single via 33 is shown in FIG. 1D.

In order to form these conductive vias 33, holes 35 are engraved fromthe upper face F4 of the handle 21 until reaching portions of the upperlevel M4 of metallizations of the interconnection structures 7. By wayof example, the width or diameter of the holes 35 is approximately 70μm. An insulating layer 37, for example a layer of silicon oxide,silicon nitride and/or silicon oxynitride, is formed on the side of theupper face F4 of the handle 21 so as to cover the handle 21, the wallsand the base of the holes 35. The portions of the insulating layer 37that are arranged at the base of the holes 35 are removed in order toexpose corresponding portions of the upper level M4 of metallizations. Aconductive layer 39, for example made of a metal such as copper ortungsten, is then formed on the walls and the base of each hole 35. Byway of example, the conductive layer 39 is formed by deposition on theside of the upper face F4 of the handle 21, and is then removed byengraving while leaving in place, on the walls and the base of each hole35, portions of this layer 39 forming a conductive via 33. During theengraving of the conductive layer 39, an annular portion 41 of the layer39 may be left in place around each via 33, on the upper face F4 of thehandle 21. In this embodiment, portions of the conductive layer 39 arealso left in place on the upper face F4 of the handle 21, level with acentral portion of each chip 5, so as to form conductive tracks 43 andconductive pads 45 there. The tracks 43 extend from the vias 33 as faras the pads 45, and conductive balls 47 may be formed on the conductivepads 45. Thus, each ball 47 is connected electrically to a portion ofthe upper level M4 of metallizations of an interconnection structure 7.

In a step that is not illustrated, the wafer 19 provided with the handle21 and with the carrier 29 is sliced along the contours of each chip 5in order to obtain a plurality of individualized chips 5.

As has been indicated previously, delaminations may occur from the edgeof a chip 5, at the bonding interface of the handle 21 to the wafer 19,and may propagate as far as a conductive connecting via 33 and damagesame.

One embodiment of a method for manufacturing a back-illuminated chipwill now be described in relation to FIG. 2.

FIG. 2 is a schematic cross-sectional view of the wafer 19 provided withthe thinned handle 21 and with the carrier 29 in a step following thestep described in relation to FIG. 1C. As is the case for FIGS. 1A to1D, FIG. 2 shows a portion of only one of the chips 5 forming a part ofthe semiconductor die 3.

The portion of chip 5 shown in FIG. 2 comprises the same elements asthat described in relation to FIG. 1D. Furthermore, an annular trench 49has been formed by engraving from the upper face F4 of the handle 21.Each chip comprises an annular trench 49 arranged at its periphery so asto surround all of the conductive connecting vias 33 of this chip 5. Thetrenches 49 extend from the upper face F4 of the handle 21 and passthrough the entire thickness of the handle 21. More particularly, thetrenches 49 pass through the bonding interface of the handle 21 to thewafer 19, that is to say the interface between the two layers of siliconoxide 17 and 23 in this example. The annular trenches 49 preferably donot penetrate into the interconnection structures 7, whichadvantageously makes it possible not to cut the electrical connectionsthat are present in these interconnection structures. By way of example,the annular trenches 49 penetrate into the insulating layer 17 overapproximately a quarter of its thickness. The width of each trench 49 isfor example between 5 and 30 μm.

Advantageously, the trenches 49 are engraved from the upper face F4 ofthe handle 21 in a step in which it had already been provided to engravethe holes 35 of the vias 33 from this upper face F4.

According to one preferred embodiment, the annular trenches 49 and theholes 35 are advantageously formed during one and the same step ofengraving, for example by plasma engraving. For this, an engraving maskcomprising apertures at the location of the holes 35 and the trenches 49is formed on the upper face F4 of the handle 21. The width of theapertures corresponding to the holes 35 is selected so as to be greaterthan that of the apertures corresponding to the trenches 49, such thatthe holes 35 are deeper than the trenches 49. Thus, in this embodiment,the manufacturing method that gives the structure in FIG. 2 does notcomprise an additional step with respect to the method that gives thestructure in FIG. 1D.

According to another embodiment, the trenches 49 are formed during afirst step of masking, engraving and removing the mask, and the holes 35are formed during a second step of masking, engraving and removing themask. Thus, in this embodiment, the method that gives the structure inFIG. 2 comprises just one additional step of masking/engraving withrespect to the method described in relation to FIGS. 1A to 1D.Preferably, the first step of masking/engraving is performed before thesecond step of masking/engraving in order to prevent portions of themask from the first step from remaining in the holes 35. Thus, the holes35 are not contaminated or damaged by the presence of such portions ofmask.

Once the holes 35 and the trench 49 have been engraved, the insulatinglayer 37, the vias 33, and optionally the tracks 43 and the pads 45 areformed in the manner described in relation to FIG. 1D. Thus, after thestep of forming the insulating layer 37, the walls and the base of thetrench 49 are covered with the insulating layer 37. Furthermore, thesesteps are carried out for example in such a way that no portion of theconductive layer 39 remains in the trenches once the formation of thevias 33 has been completed.

In a subsequent step that is not illustrated, the wafer 19 provided withthe handle 21 and with the transparent carrier 29 is sliced along thecontours 51 of each chip 5 in order to obtain a plurality ofindividualized chips 5, each of which comprises an annular trench 49 atits periphery.

Advantageously, when a delamination occurs from the edge of a chip 5 atthe bonding interface of the handle 21 to the wafer 19, thisdelamination is stopped at the annular trench 49 and is therefore unableto reach a conductive connecting via 33.

FIG. 3 is a plan view of a chip 5 having the structure in FIG. 2 afterslicing. In this figure, a single track 43, a single pad 45 and a singleball 47 are shown, it being understood that, in practice, the chipcomprises several conductive tracks, pads and balls. These pads andballs are organized for example in the form of matrices inside a ring ofvias 33.

The annular trench 49 is arranged on the perimeter of the chip 5, thatis to say at the periphery of the chip 5, for example at a substantiallyconstant distance d from the edge 51 of the chip 5. This distance d maybe between 5 and 30 μm, for example 15 μm. The conductive vias 33 areformed in a central portion of the chip 5 that is delimited by theannular trench 49. A distance D, for example greater than 5 μm, or evengreater than 10 μm, separates each via 33 from the trench 49. Thisdistance is chosen to be large enough to prevent portions of theconductive layer 39 from being present in the trench 49 after theformation of the conductive vias 33. By way of example, the chip has arectangular surface, for example a surface of a few square millimeters,for example approximately 3 mm*2.5 mm.

Specific embodiments have been described. Various variants andmodifications will be apparent to a person skilled in the art. Inparticular, the stack of optional insulating layers 11, 13, 15 and 17formed on the interconnection structure 7 and to which the handle 21 isbonded may comprise other insulating layers. Conversely, at least someof these optional insulating layers may be omitted.

The number and/or the order of the steps of the method described abovein relation to FIGS. 1A to 1C and 2 may be adapted by a person skilledin the art. For example, in the step in which the transparent carrier 39is bonded to the side of the back face F2 of the semiconductor layer 3,a step of heat or ultraviolet treatment may be provided when theadhesive 31 is made of a polymer material. Furthermore, after theformation of the trenches 49, the vias 33, the tracks 43 and the pads45, an insulating passivation layer, for example made of resin, may bedeposited on the side of the upper face F4 of the handle 21. Thispassivation layer may then form bridges that close the trenches 49 andthe holes 35 at this face F4.

Moreover, the conductive connecting vias 33 formed through the handle 21may extend as far as portions of an intermediate level of metallization,for example M3 or M2, or of a lower level of metallization, for exampleM1, of the interconnection structure 7 of the chip.

Although it has not been described, after the step of slicing or sawingthe wafer 19 provided with the handle 21 and with the carrier 29, thechip 5 may be mounted on a printed circuit board or an interposer board,each ball 47 then being in contact with a conductive surface of thisboard.

The semiconductor die may be replaced by an SOI (semiconductor oninsulator) die, comprising a semiconductor layer resting on aninsulating layer, itself resting on a semiconductor substrate, thesemiconductor layer then being on the side of the front face of the SOIdie.

1. A method for manufacturing image sensor chips, comprising: a) forminga wafer comprising a semiconductor die, interconnection structuresarranged on a front face of the semiconductor die, and matrices ofpixels formed in the semiconductor die with circuit elements formed atsaid front face that are connected to said interconnection structures;b) bonding a first face of a handle to the wafer facing saidinterconnection structures; c) for each image sensor chip, opening, froma second face of the handle, an annular trench surrounding each matrixof pixels, the annular trench passing through an entire thickness of thehandle; and d) slicing the wafer for separate the image sensor chips,wherein an edge of each image sensor chip is located beyond the annulartrench of said image sensor chip.
 2. The method according to claim 1,wherein step b) further comprises forming a first layer of silicon oxideat the first face of the handle, and wherein step c) further comprisesopening each annular trench to extend completely through the first layerof silicon oxide.
 3. The method according to claim 2, wherein step a)further comprises forming a second layer of silicon oxide on theinterconnection structures; and wherein step b) further comprisesbonding the first layer of silicon oxide to the second layer of siliconoxide; and wherein step c) further comprises opening the annular trenchto extend completely through the first layer of silicon oxide and atleast partly through a thickness of the second layer of silicon oxide.4. The method according to claim 1, wherein step a) further comprisesforming a layer of silicon oxide on the interconnection structures;wherein step b) further comprises bonding the handle to the layer ofsilicon oxide; and wherein step c) further comprises opening the annulartrench to extend at least partly through a thickness of the layer ofsilicon oxide.
 5. The method according to claim 1, further comprisingforming conductive vias by: for each image sensor chip, opening holesfrom the second face of the handle to reach portions of a level ofmetallization of the interconnection structure; forming an insulatinglayer on the second face of the handle, said insulating layer coveringwalls and a base of the holes and of the annual trench; removingportions of the insulating layer at the base of the holes; and forming aconductive layer on the walls and the base of each hole.
 6. The methodaccording to claim 5, wherein the annular trench and the holes areopened simultaneously.
 7. The method according to claim 1, wherein adepth of the annular trench does not reach the interconnectionstructures.
 8. The method according to claim 1, further includingthinning the semiconductor die from the back face after bonding of thehandle.
 9. The method according to claim 8, further including, betweensteps c) and d) and before thinning the semiconductor die, bonding atransparent carrier to the wafer on the side of the back face of thesemiconductor die.
 10. A method, comprising: a) forming a wafer whichincludes a semiconductor substrate, integrated circuits for a pluralityof pixel arrays located in the semiconductor substrate and aninterconnection layer arranged over the semiconductor substrate; b)bonding a first face of a handle to the interconnection layer; c)opening, from a second face of the handle, a plurality of annulartrenches, wherein each annual trench surrounds a corresponding one ofthe pixel arrays and passes completely through a thickness of thehandle; and d) slicing the wafer and handle to form a plurality of imagesensor chips, each image sensor chip including one of the pixel arrays,and wherein a peripheral edge of each image sensor chip surrounds and isoffset from the annular trench.
 11. The method according to claim 10,wherein step b) further comprises forming a first layer of silicon oxideat the first face of the handle to assist with bonding the handle to theinterconnection layer, and wherein step c) further comprises opening theannular trench to extend completely through the first layer of siliconoxide.
 12. The method according to claim 10, further comprising forminga first layer of silicon oxide on the interconnection layer and forminga second layer of silicon oxide at the first face of the handle; whereinstep b) further comprises bonding the layers of silicon oxide to eachother when bonding the handle to the interconnection layer the secondlayer of silicon oxide; and wherein step c) further comprises openingthe annular trench completely through the second layer of silicon oxideand at least partly through a thickness of the first layer of siliconoxide.
 13. The method according to claim 10, wherein step a) furthercomprises forming a layer of silicon oxide on the interconnectionstructures; wherein step b) further comprises bonding the handle to thelayer of silicon oxide; and wherein step c) further comprises openingthe annular trench at least partly through a thickness of the layer ofsilicon oxide.
 14. The method according to claim 10, further comprisingforming conductive vias which extend completely through the handle toreach portions of a level of metallization of the interconnection layer.15. The method according to claim 14, wherein forming the conductivevias comprises: opening holes from the second face of the handle toreach the level of metallization; forming an insulating layer coveringwalls and a base of each of the holes; removing portions of theinsulating layer at the base of the holes; and forming a conductivelayer on the walls and the base of each of the holes.
 16. The methodaccording to claim 15, wherein the annular trenches and the holes areopened simultaneously.
 17. The method according to claim 15, wherein adepth of each annular trench does not reach the interconnection layer.18. The method according to claim 10, further including thinning thesemiconductor substrate from a back face after bonding of the handle.